Memory cells, especially flash memory and corresponding flash memory cells, are at the heart of many electronic products. Flash memory is now popular consumer memory for smart phones, cameras, memory sticks and so on, and are important especially for portable electronics. Over the last few decades, such memory cells have undergone aggressive scaling to achieve a dramatic reduction in cell size. Recently, the 20 nm half pitch (F) mark has been reached for flash memory cells (ITRS, 2012). This has been accompanied by reduction of tunnel oxide thickness to improve programming/erasing performance. Furthermore, the interpoly dielectric thickness has been reduced to keep the capacitance coupling ratio at an almost constant value, thereby achieving acceptable ratios between the voltages of the control gate and the floating gate (FG). Downscaling of metal-oxide-semiconductor (MOS) flash memory to below 10 nm faces challenges, because alternative molecules proposed to replace MOS flash memory (Joachim et al., 2000) suffer from low electrical conductivity, high resistances, low device yields and finite thermal stability. This limits their ability to integrate into current MOS technologies. There are a number of significant barriers to the realisation of devices within conventional MOS technologies (H. Zhu et al., 2013, P.-C. Chen et al., 2008, J. Shaw et al., 2012, M.-L. Seol et al., 2012, S. J. Tans et al., 1998).
Examples of metal-oxide-semiconductor field effect transistors (MOSFETs) can be found in US 2013/0049140.
Molecular electronics was first conceived in 1973 when Aviram and Ratner speculated about employing organic molecules as components in electronic circuits (A. Aviram and M. Eatner, 1974). The first molecular-based random access memory (RAM) used rotaxanes (J. E. Green et al., 2007). A concentrated effort has been associated with developing novel molecular materials with electron-transport and/or electron-storage properties for decreasing the size of components of future electronic devices to nanometer and sub-nanometer dimensions or for novel applications (C. Joachim et al., 2000; J. E. Green, et al., 2007; A. H. Flood et al., 2004; S. J. Tans et al., 1998). It is generally thought that using individual molecules as the electrical elements in devices has the potential to revolutionize modern technologies, and is necessary for decreasing the size of the components of future electronic devices down to nanometer and sub-nanometer dimensions.
Chemical synthesis in combination with molecular self-assembly of redox-active molecules can yield a very regular distribution (spatially and energetically) of charge-storage centres (T. Pro et al., 2009) and allow scaling of a floating gate in a memory cell down to a few nanometers, as shown using organic redox-active molecules based on ferrocene and porphyrin (J. Shaw et al., 2011). However, these molecules display low retention time due to the small associated redox potentials. Organic molecular electronics also suffer from high resistance, low power and low performance, as well as problematic fabrication, integration into current technology, reproducibility and reliability. Organic molecules are not compatible with the high temperatures required to manufacture optimised MOS technologies with high performance, high density and small real estate.
Conventional memory devices use poly-silicon as the charge storage FG layer. Silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile molecular memories (NVMMs) have a nitride layer of Si3N4 as FG but suffer significant variability due to the random number and position of traps and trapped charges. Specifically, nitride cells have poorer program/erase properties than other cell types (Memory Strategies International, 2013).
Trap-rich dielectrics and metallic nano-clusters have also been suggested for use in electronic devices. However, both technologies exhibit problems. Charge-trap memories show large variation in trap-density and trap-energy (B. Kumar et al., 2006). The size and density of nano-clusters is difficult to control, which precludes their ultimate miniaturisation (J. Shaw et al., 2009). It is desirable to avoid such non-uniformity in electronic devices. It is especially desirable to avoid non-uniformity in flash memory cells, because it limits the yield and necessitates complex writing protocols.
The further scaling of NAND flash memory devices, for example, faces significant challenges, including:                (i) strong coupling between the poly 1 gates that can result in cross-talk and errors in write and read operation, particularly in multilevel devices; and        (ii) charge loss from the poly 1 gate due to trap assisted tunneling in the tunneling oxide, which is exacerbated in the write/erase cycling process.        
These challenges highlight the need for an alternative to traditional floating gate technology. Of particular importance is the hard limit to scaling of the poly 1 to poly 1 pitch along the word line, due to the oxide/nitride/oxide (ONO) thickness on the floating gate side wall. One attempt at solving the above problems was proposed using charge trapping memories (ITRS, 2012), and is based on storing charge inside a silicon nitride of a high-k dielectric. Although the charge trapping approach has had some success, for example suppression of floating gate to floating gate disturbance, immunity to localized defects in the tunneling oxide and corresponding charge leakage, simple integration for embedded memory applications and good scalability, the approach has some significant limitations. Among these problems is that the random number and position of the traps creates significant variability in the threshold voltage of the programmed flash cells, particularly in the case of multilevel operation. This problem occurs despite progressive adaptive writing algorithms (S. M. Amoroso et al., 2010). The problem will be increasingly difficult to overcome as the size decreases.
The use of microcrystal memories has also been suggested as an alternative approach to charge trapping memory cells. In these devices, the charge is stored on semiconductor microcrystals embedded in the cell gate dielectric (L. Forbes, U.S. Pat. No. 5,852,306). Although multiple charges can be stored on a single microcrystal, these sorts of memory also suffer from acute statistical variability due to the size distribution of the microcrystals (typically in the range 2-5 nm). So, different preparation conditions, such as different injection conditions, must be used for microcrystals with different sizes. There is also variation in the memory cell behavior due to the variation in size, number and position of the microcrystals. In combination with the size of the microcrystals, these problems make it difficult to scale memory cells below the 20 nm half pitch mark.